GenAlpha
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Member of Technical Staff — Analog IC
Headquartered in San FranciscoEngineeringFull-time
GenAlpha brings AI to silicon’s toughest challenges. We’re an early-stage startup, founded in 2024 by experts in semiconductors, ML and AI, and backed by Silicon Valley’s best VCs. AI is driving demand for more chips than ever, just as Moore’s Law runs out. Each new chip is harder to design than the last: more complex, more costly and more laborious at every node.
The role
Design and verify circuits, lead design reviews, and drive the insights embedded in our next-gen AI Designers.
What you’ll do
Expect to work on any and all of:
- Design, simulate and verify analog and mixed-signal blocks from spec through post-layout sign-off. Examples include amplifiers, references, LDOs, comparators, data converters, PLLs and clocking, and high-speed I/O front ends
- Help set block specs and run architecture and feasibility studies, using behavioral models (Verilog-A, MATLAB, Python)
- Build designs and demos that hold up to a professional design review, including PVT corners, Monte Carlo, noise and stability, post-layout performance, reliability, and a clean DRC/LVS
- Design reusable silicon IP, and take designs through tape-out and silicon validation when a project needs it
- Guide and review layout for goals including floorplanning, matching and symmetry, parasitics, EM/IR and reliability. Incorporate those reviews and lessons into future AI Designers
- Write the specs, testbenches, reference answers and grading criteria our AI is evaluated against
- Work with our software and AI engineers on the tools themselves. That includes explaining circuits clearly to people who have never designed one
- Work on a wide range of circuits, including customer design projects on SerDes, ADCs, PLLs, other data conversion, analog computation, and more
What we’re looking for
- Hands-on analog or mixed-signal IC design experience, from industry, graduate research, or both. You have taken blocks from spec through schematic, layout review and post-layout verification
- Solid transistor-level fundamentals: device behavior in modern FinFET, planar or FD-SOI processes, noise, mismatch, linearity, feedback and stability, and the tradeoffs between them
- Comfort building testbenches and running the full set of analyses: DC, AC, transient, noise, loop stability, PVT corners and Monte Carlo
- Fluency with pro-grade custom design flows: Cadence (Virtuoso, Spectre) and/or Synopsys (Custom Compiler, HSPICE/PrimeSim), plus physical verification and extraction (Calibre, ICV, StarRC, Quantus)
- Experience reviewing and driving custom IC layout, through design review, process and design knowledge
- Clear communication with two audiences: other circuit designers, and software and AI engineers who aren’t.
- BS, MS or PhD in Electrical Engineering or a related field, or equivalent experience
- You do not need to write software. Scripting (Python, SKILL, Tcl) helps, but nobody here will give you a coding interview
Bonus points for:
- Tape-outs at advanced nodes, and silicon bring-up or lab characterization
- Depth in one or more of data converters, PLLs and clocking, SerDes and high-speed I/O, power management, or RF
- Having already used AI tools in your own design work, and having opinions about where they help and where they don’t
Not every bullet? Apply anyway.
Very few candidates match every line on a job post. If you’re a strong analog designer and the idea of defining how AI changes this job excites you, we’d like to hear from you, even if your background doesn’t match this list line for line. Please don’t count yourself out before we’ve talked.
Email careers@ →
#Culture
We’re a small, all-technical team, all working at the forefront of turning AI into next-gen silicon. We’re headquartered in San Francisco and built for close collaboration. We value engineers who are unafraid to try and learn new and valuable tools, wherever they can be found. Past experience in customer-facing engineering roles is a plus. Desire to grow into engineering leadership is a plus. Desire to work in a rapidly changing, early stage startup environment is a must.
Everyone on the GenAlpha team gets the same title: Member of Technical Staff. Compensation varies with experience and fit, with competitive salaries and meaningful equity for all team members. We provide the best medical, dental, and vision coverage we can get, for both you and family. We sponsor work visas and permanent residency applications for qualified international candidates.
Req ID: R7